# SPI protocol

## Introduction

* SPI = Serial Peripheral Interface , its a Master/Slave (Controller/Peripheral) protocol thats synchronous (having a clk)
* popular and easy to implement (basically using a shift register to shift in/out data thats it!)
* serial in natue and the max theoretical speed = clk/2&#x20;
* used in device to device comminucation over short distaces
* one master , multiple slave  (Multimaster is possible and collision / arbitration is also required NSS as input is used for this in stm32 )

## configuration / connection

<figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2FxlK7MmSBi23qBSASkxju%2F205973_Fig_01.svg?alt=media&#x26;token=88ad41f9-a2d2-48c9-8f7e-fca6f75ebaa8" alt=""><figcaption><p>master slave </p></figcaption></figure>

* CS = Chip select (NSS) , SCLK = clk , MISO = Master In slave out (salve sends data and master recieves) , MOSI = Master Out Slave In (Master send data Slave receives data)
* CS is pulled low by master of corresponding slave to start communication
  * different configuration : full duplex , half duplex simplex

    * full duplex : bidirectional communication at the same clock pulse connection same as above
    * half duplex : single data line to either tx or rx data , single directional communication as configured&#x20;
    * simplex: unidirectional communication&#x20;

    <figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2FRuHuj713JPWPV7kkCMGN%2Fhalf-duplex.jpg?alt=media&#x26;token=529a694d-aa00-4c3c-b664-6174ee7393aa" alt=""><figcaption><p>haf duplex mode</p></figcaption></figure>

    <figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2F1HaMPID7ExUQtkldruo5%2Fsimplex.png?alt=media&#x26;token=c65d3c02-27f5-4fb6-9b1a-ed8e1a772fa2" alt=""><figcaption><p>simplex mode</p></figcaption></figure>
* 8 bit register or 16/12 depending on the shift register used&#x20;

ex:  stm32f407vgtx has 16bit shift register

* Software slave management / hardware slave management is possible using SSI and SSM in stm32&#x20;

## Details

### CPOL

* Clock polarity sets the clock format : **cpol=0** clock state is normally low and is pulled up/down when active **(active high)**
* **cpol =1** , idle state is high , pulled low during the transmission **(active low)**

### CPHA

* determines when to sample data , rising edge or falling edge and when to send the data ring or falling edge
* data should be sampled when its not transitioning to prevent reading it wrongly
* **cpha =  0 , data sampled at leading edge of clock**
* **CPHA = 1 ,  data sampled at trailing edge of clock**

<figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2FCQ7pod18OwqxQ6ta5YBz%2Fspimode0.jpg?alt=media&#x26;token=2c08fc41-f9ec-4f4b-84ee-8f58c13d1b6b" alt=""><figcaption><p>SPI mode 0</p></figcaption></figure>

<figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2FUtKyuAkumZwodNnZlq0z%2Fspi1.jpg?alt=media&#x26;token=4d8ba792-96ba-42b2-b9d9-69efcc171639" alt=""><figcaption><p>SPI mode 1</p></figcaption></figure>

<figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2FeIQP1NF2EnQ3FKMVV8mA%2Fspi2.jpg?alt=media&#x26;token=de6be167-961d-41fa-8f92-ff5d221f748c" alt=""><figcaption><p>SPI mode 2</p></figcaption></figure>

<figure><img src="https://2053013877-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FKg8J6xCJHYTeKrG8eHmB%2Fuploads%2Fagk4S0eHZIksv6ATQRfr%2Fspi3.jpg?alt=media&#x26;token=aef4259a-8925-488d-94a6-536eae6d7034" alt=""><figcaption><p>SPI mode 3</p></figcaption></figure>

### Data frame format

* 8 bit normally and 16 bit if configured&#x20;

## Usage and limitations

* Used widely everywhere due to the ease of implementation and since no complex data frame is present its simple
* Max theoretical speed is clk/2 , max distance is low (intended for PCB and have no differential pair signal so detection of error is hard also usually high frequency) , max distance in few meters
* High frequency high data transfer rate , Mbps

## Types of SPI&#x20;

* TI and Motorola SPI are slightly different SPI modes&#x20;

## references:

{% embed url="<https://training.ti.com/ti-precision-labs-adcs-spi-serial-modes-clock-data?context=1139747-1140267-1128375-1146616-1148195>" %}

{% embed url="<https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html>" %}

{% embed url="<https://en.wikipedia.org/wiki/Serial_Peripheral_Interface>" %}

## video:

{% embed url="<https://www.youtube.com/watch?ab_channel=nandland&v=ba0SQwjTQfw>" %}
