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On this page
  • Introduction
  • configuration / connection
  • Details
  • CPOL
  • CPHA
  • Data frame format
  • Usage and limitations
  • Types of SPI
  • references:
  • video:
  1. Embedded systems

SPI protocol

Notes on SPI protocol

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Last updated 2 years ago

Introduction

  • SPI = Serial Peripheral Interface , its a Master/Slave (Controller/Peripheral) protocol thats synchronous (having a clk)

  • popular and easy to implement (basically using a shift register to shift in/out data thats it!)

  • serial in natue and the max theoretical speed = clk/2

  • used in device to device comminucation over short distaces

  • one master , multiple slave (Multimaster is possible and collision / arbitration is also required NSS as input is used for this in stm32 )

configuration / connection

  • CS = Chip select (NSS) , SCLK = clk , MISO = Master In slave out (salve sends data and master recieves) , MOSI = Master Out Slave In (Master send data Slave receives data)

  • CS is pulled low by master of corresponding slave to start communication

    • different configuration : full duplex , half duplex simplex

      • full duplex : bidirectional communication at the same clock pulse connection same as above

      • half duplex : single data line to either tx or rx data , single directional communication as configured

      • simplex: unidirectional communication

  • 8 bit register or 16/12 depending on the shift register used

ex: stm32f407vgtx has 16bit shift register

  • Software slave management / hardware slave management is possible using SSI and SSM in stm32

Details

CPOL

  • Clock polarity sets the clock format : cpol=0 clock state is normally low and is pulled up/down when active (active high)

  • cpol =1 , idle state is high , pulled low during the transmission (active low)

CPHA

  • determines when to sample data , rising edge or falling edge and when to send the data ring or falling edge

  • data should be sampled when its not transitioning to prevent reading it wrongly

  • cpha = 0 , data sampled at leading edge of clock

  • CPHA = 1 , data sampled at trailing edge of clock

Data frame format

  • 8 bit normally and 16 bit if configured

Usage and limitations

  • Used widely everywhere due to the ease of implementation and since no complex data frame is present its simple

  • Max theoretical speed is clk/2 , max distance is low (intended for PCB and have no differential pair signal so detection of error is hard also usually high frequency) , max distance in few meters

  • High frequency high data transfer rate , Mbps

Types of SPI

  • TI and Motorola SPI are slightly different SPI modes

references:

video:

📈
SPI communication basics (modes)TI Training
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Introduction to SPI Interface | Analog Devices
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Serial Peripheral InterfaceWikipedia
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master slave
haf duplex mode
simplex mode
SPI mode 0
SPI mode 1
SPI mode 2
SPI mode 3